Chips

算能科技 SOPHGO (formerly Sophon)

Cores inside · XuanTie C920 ×64 (licensed IP, integrated)

Cores

64× T-Head XuanTie C920, 4 cores/cluster × 16 clusters; 64KB L1 per core, 1MB L2 per cluster, 64MB system-level L3

ISA

RV64GCV + RVV 0.7.1 (128-bit)

Performance

2.0GHz base clock; vendor-claimed 1 TFLOPS FP64, 120W TDP; independent review: single-core performance roughly 5–10× the RISC-V hardware available at the time, while an x86 server CPU is about 4–8× faster in multithreaded workloads

Target use

Servers / HPC / AI inference

First shown

2022-12

the first 64-core RISC-V server chip; In volume production; the world's first commercially shipping 64-core RISC-V CPU, and the first to move RISC-V onto the mainstream general-purpose server/HPC track.

Ventana Micro Systems (acquired by Qualcomm 2025-12)

NoteVentana was acquired by Qualcomm in 2025-12; the product line may change and the part may not be purchasable

Cores inside · Ventana in-house 8-wide out-of-order cores ×16 per chiplet

Cores

8-wide out-of-order, 16 cores/cluster, up to 8 chiplets = 128 cores; 48MB L3 per cluster

ISA

RV64GC + Vector extension (V1 does not state an RVA profile)

Process

5nm

Performance

3.6GHz; vendor positions it against x86 servers, with RAS/IOMMU/AIA

Target use

Data centers / 5G / automotive

First shown

2022-12

Supplied as IP and chiplets (the company has been acquired by Qualcomm); V1 was the first product to turn RISC-V into a data-center-class chiplet and defined the 128-core scalable route.

Ventana Micro Systems (now part of Qualcomm)

NoteVentana now belongs to Qualcomm; the product line may change and the part may not be purchasable

Cores inside · Ventana in-house cores ×32 per chiplet (UCIe)

Cores

15-wide decode/dispatch out-of-order; 32 cores/chiplet, up to 6 chiplets = 192 cores; UCIe interconnect, 5TB/s NoC

ISA

RVA23 + RVV 1.0 (512-bit) + Vector Crypto

Process

4nm（TSMC）

Performance

3.6GHz; IPC +20% over V1, +40% overall; 192-core SPECint2017rate about 23% higher than a 128-core Bergamo (360W, vendor simulation)

Target use

Data centers / AI host CPU

First shown

2023-11

IP/chiplets (the company has been acquired by Qualcomm); V2 was the earliest data-center-class implementation of RVA23 with 512-bit vectors, later acquired by Qualcomm to bolster its CPU roadmap.

Tenstorrent

Cores inside · In-house Ascalon-X IP cores ×8

Cores

8× Ascalon-X (single cluster)

ISA

RVA23 + RVV 1.0

Performance

8-core Ascalon-X cluster (official QEMU machine type), RVA23; first-party pages do not state the clock speed

Target use

Server software ecosystem / AI hosts

Development platform (modelled upstream in QEMU, can run OpenSBI/Linux); Atlantis is Tenstorrent's RVA23 silicon validation platform, taking Ascalon from IP to a Linux-capable system.

Rivos (acquired by Meta 2025-10)

NoteAcquired by Meta in 2025-10 and never sold as a standalone product; not available to buy

Cores inside · Rivos in-house 64-bit RVA23 cores

Cores

In-house 64-bit RVA23 CPU @3.1GHz + Rivos SIMT GPGPU; chiplet architecture

ISA

RVA23

Performance

3.1GHz; unified memory HBM3e + DDR5 RDIMM; integrated Ultra Ethernet NIC; CUDA compatible (recompile, not redesign)

Target use

Data-center AI training/inference

Absorbed into Meta and never launched independently; Rivos was one of the few teams with an in-house RVA23 server core plus GPU, and after the Meta acquisition became the CPU foundation of its MTIA roadmap.

Akeana (now part of Qualcomm)

NoteAkeana now belongs to Qualcomm, and this is a silicon-validation test chip rather than a product for sale

Cores inside · Akeana 5000 series IP cores ×8

Cores

8× 5000-series out-of-order cores (6–10 issue, 12-stage), 2×2 CHI mesh, 4MB L3 shared per 2 cores

ISA

RVA23 + RVV 1.0 (2×128-bit) + Vector Crypto

Process

4nm

Performance

The 5000-series IP is specified at 3GHz, 20–25 SPECint2006/GHz; Alpine includes LPDDR5×2 and PCIe Gen5 x4

Target use

Servers / SmartNIC / storage and memory acceleration

First shown

2025-10

Taped out (2025-12), sampling in 2026; Alpine is the highest-performance RVA23 server-class test chip of 2025, showing that a small team can build a Neoverse-class SoC.

算能科技 SOPHGO

Cores

8-wide out-of-order single-core IP (multi-core capable)

ISA

RV64GCVH + RVV 1.0 + RVA23 (IOMMU/AIA)

Performance

SPECint2006 >20/GHz (vendor claim, positioned against Cortex-X1)

Target use

Servers / high-performance computing IP licensing

First shown

2025-06

Announced (2025-06-30, member licensing); SOPHGO opened its in-house high-performance core for licensing, giving domestic server cores one more IP supply route.

阿里巴巴达摩院玄铁（XuanTie）

Cores

Core count and clock speed not disclosed by the vendor (designed as server-class multi-core clusters)

ISA

RVA23 + RVV 1.0 (512-bit) + 8 TOPS Matrix; Vector Crypto, Zacas, Zama16b, Smmtt, CoVE, RAS, AIA

Performance

SPECint2006 >17/GHz (XuanTie website); 8 TOPS Matrix engine; TAGE branch prediction, private L2, tunable prefetch

Target use

Servers / AI-HPC

First shown

2025-02

Shipping in volume (since 2025-03); DAMO Academy's first server-class CPU, natively fusing vector and matrix engines — a landmark product for domestic RISC-V moving onto the mainstream server track.

阿里巴巴达摩院玄铁（XuanTie）

Cores

Single-core IP: 12-stage multi-issue out-of-order, up to 2.5GHz, optional out-of-order vector unit (VLEN 128/256); supports multi-core multi-cluster, SG2042 integrates 64 cores

ISA

RV64GCV + RVA22 + RVV 1.0; AMBA 4.0 ACE/AXI, supports BF16/FP16/FP32

Performance

Up to 2.5GHz (2.0GHz in SG2042); AI performance up to 3.8× the previous generation (vendor claim)

Target use

Servers / edge AI / autonomous driving

First shown

2023-11

In volume production; C920 provides the compute foundation of SG2042 and is the core IP behind the domestic 64-core server chips that actually shipped.

SiFive

Cores

4-issue, 13-stage out-of-order; up to 16 cores per cluster, multi-cluster capable

ISA

RVA22 + RVV 1.0 (2×128-bit) + Vector Crypto

Performance

>13 SPECint2006/GHz; >50% improvement over P550, better efficiency per area than Cortex-A78 (vendor claim)

Target use

Edge servers / consumer application processors

First shown

2023-05

In volume production / IP licensed; P670 is SiFive's mainstay for 16-core-class application processors, adopted by domestic SoCs such as SOPHGO SG2380.

SiFive

Cores

6-issue out-of-order; up to 32 cores per cluster

ISA

RVA23 + RVV 1.0 (2×128-bit) + Vector Crypto

Performance

>18 SPECint2006/GHz; +50% single-thread over the previous generation (vendor claim)

Target use

High-performance application processors / data centers

First shown

2023-08

In volume production / IP licensed; P870 brings RISC-V single-thread performance to the 18/GHz level and sets the baseline for high-end RVA23 IP.

SiFive

Cores

6-issue out-of-order; AMBA CHI interconnect, up to 64 clusters / 256 cores (on-die or chiplet)

ISA

RVA23 + RVV 1.0

Performance

>2 SPECint2017/GHz; supports CXL, CHI C2C, cluster-level DVFS and RAS

Target use

Data centers (storage, web, video streaming)

First shown

2024-08

In volume production / IP licensed; the first RISC-V IP explicitly built around data-center requirements with CHI/RAS/CXL, scaling to 256 cores across chiplets.

Tenstorrent

Cores

Single-core IP (scalable across multi-core clusters)

ISA

RVA23 + RVV 1.0 + Hypervisor/AIA/IOMMU + RAS

Process

Samsung SF4X

Performance

>22 SPECint2006/GHz; >2.3 SPECint2017/GHz; >3.6 SPECfp2017/GHz; >2.5GHz

Target use

Servers / AI infrastructure / automotive HPC

In production / licensable (since 2025-12); Ascalon pushes RISC-V single-core SPECint to the 22/GHz level, among the highest-performing server-class cores in open IP.

Tenstorrent

Cores

Single-core IP (compact, aimed at infrastructure/edge)

ISA

RVA23

Performance

70% of Ascalon X performance at 50% of the area (vendor claim)

Target use

AI infrastructure / edge / automotive

First shown

2026-10

Announced (2026-10); Ascalon S halves the area of the server-class core, targeting cost-sensitive settings such as DPUs and the edge.

Akeana (acquired by Qualcomm 2026-10)

NoteAkeana was acquired by Qualcomm in 2026-10; the roadmap may change and licensing may not be available

Cores

1–4 issue in-order, optional 12-stage out-of-order; SMT up to 4 threads

ISA

RV64 + RVV (≤512-bit); configurable RVA22/RVA23

Performance

>2GHz fmax; 5–18 SPECint2006/GHz (vendor claim)

Target use

Consumer / AI PC / automotive domain controllers

First shown

2024-08

IP available for licensing (the company has been acquired by Qualcomm); the 1000 series is Akeana's 64-bit core for mainstream applications, where SMT plus vector lets it compete with Neoverse N1 at the same area.