News
2026
Lanxin Computing unveils Zhitong fusion supernode, taking LX500 from single systems to clusters
At the 2026 RISC-V China Summit, Lanxin Computing launched a Zhitong fusion supernode, extending its LX500-based RISC-V AI compute from a single chip and server to cluster-level infrastructure. LX500 integrates 48 RISC-V cores (32 performance, 16 efficiency) with AI vector and matrix engines for 75 TOPS INT8, shares DDR5 through a unified memory architecture and supports CXL, tuned for time-to-first-token, prefill and long-context inference. The lineup now spans the LX500 chip, the Lenovo Wentian WR5219 G5 server, the LX5000 all-in-one and the supernode, and the company says Qwen, DeepSeek and Kimi models are already adapted — RISC-V servers are starting to ship as a full chip-system-cluster stack.
UltraRISC details UR-CP400: an RVA23 server-class core IP shipping in Q1 2027
At the 2026 RISC-V China Summit, UltraRISC disclosed UR-CP400, a high-performance RISC-V core IP compliant with RVA23 and RVV 1.0, using an 8-wide out-of-order, 14-stage pipeline and exceeding 22 SPECint_base2006 points/GHz in FPGA configuration, with enhancements for multi-tenant cloud virtualization and agentic workloads; delivery is planned for Q1 2027. UltraRISC offers both core IP and multi-core CPUs, and UR-CP400's figures approach first-tier server cores, but commercial silicon is still a year out.
Alibaba DAMO Academy's XuanTie passes 6 billion shipped chips, positions C950 for data-center compute
At the 2026 RISC-V China Summit, DAMO Academy chief scientist Meng Jianyi reported that cumulative XuanTie RISC-V shipments have passed 6 billion units, that the server-class C950 core is based on RVA23 and exceeds 70 SPECint2006 points per core, and outlined a processor roadmap aimed at autonomous driving and embodied AI. DAMO stressed hardware-software co-design to move products from usable to mass-producible. For the server market, C950 is one of the few Chinese RISC-V core IPs explicitly aimed at general-purpose data-center compute, and the shipment scale shows the XuanTie ecosystem can support high-end products.
ZTE Microelectronics' Lirui Micro shows Zhufeng 200, a RISC-V CPU for AI data centers
At the 2026 RISC-V China Summit, Lirui Micro, a subsidiary of ZTE Microelectronics, showed Zhufeng 200, a high-performance RISC-V CPU for AI data centers. The chip is based on RVA23 with Hypervisor, AIA, CoVE and RVV 1.0 support, uses a 64-bit superscalar out-of-order architecture, integrates vector/matrix plus compression and crypto engines, and supports DDR5 (including MRDIMM), PCIe 6.0 and CXL 3. It targets agent clusters, inference supernode host CPUs and enterprise hybrid inference; the company says it can run 100-billion-parameter MoE models, with detailed specifications due by the end of 2026. It is the first time a carrier-affiliated Chinese chip company has positioned RISC-V explicitly as a data-center host CPU.
Tenstorrent closes $1.5B Series E at a $6.2B valuation
Tenstorrent closed a $1.5 billion Series E at a $6.2 billion post-money valuation, led by Trace Capital and Innovation X with participation from ARK Invest, Fidelity, Morgan Stanley, Sandisk and Tether Investments, among others. The company says the capital will fund volume deployment of Galaxy servers, expand inference services for open-weight models, and advance the AI and CPU IP it licenses. Tenstorrent pairs RISC-V CPUs (TT-Ascalon) with in-house Tensix AI cores across a stack that runs from a single card to superclusters, and the round adds manufacturing and delivery capacity to its data-center competition with NVIDIA.
Qualcomm acquires RISC-V startup Akeana, stepping up its AI and data-center chip push
Qualcomm has completed its acquisition of RISC-V processor design company Akeana; the deal value was not disclosed, and Akeana's IP and engineering team moved into Qualcomm wholesale to strengthen its AI and data-center position. Akeana was founded in 2021 by a team that had worked on server chips at Marvell, raised more than $100 million in August 2024, and focuses on customer-customizable RISC-V cores. It is the second time Qualcomm has taken a data-center-class RISC-V asset in-house, after Ventana.
SpacemiT launches V100: a 46-core RISC-V server CPU scalable to 92 cores in dual-socket
At the 2026 RISC-V China Summit in Shenzhen, SpacemiT launched its first server-class chip, the V100: 6 XiangShan “Kunminghu” V2R2 high-performance cores plus 40 in-house X100 efficiency cores, 46 cores in total, scalable to 92 cores across two sockets, with 8-channel DDR5 and 52 PCIe 5.0 lanes. The company calls it the industry's first compute chip fully compliant with the RISC-V server specification, with all BRS tests passed and distributions such as openEuler, openKylin, Ubuntu, Debian and Fedora installing and booting directly. It is the first time a XiangShan core has gone into a commercial server chip, and it means RISC-V servers are starting to offer general-purpose distribution delivery.
Ten years of zeroRISC: the commercial path for open-source silicon security
The Next Platform interviewed zeroRISC founder Dominic Rizzo about the decade in which he went from Google's OpenTitan project to commercializing open-source silicon. The company enters server security through an open-source Root of Trust and argues that open silicon has distinct value for confidential computing and supply-chain trust. The piece is ecosystem observation, not a product announcement.
SiFive and AMD partner to bring ROCm to RISC-V servers
At the AI Infra Summit, SiFive and AMD demonstrated ROCm 10.0 running on the SiFive BigSky platform: a P870-D as head node with a Radeon AI PRO R9700 handling inference offload, running the Gemma4-E2B model. Both companies said they will keep optimizing ROCm performance on RISC-V servers. It is the first time RISC-V servers have appeared in the official partnership view of a mainstream GPU software stack.
Canonical on how Ubuntu is preparing for RISC-V enterprise readiness
At Hot Chips 2026, Canonical silicon alliances director Gordan Markuš walked through Ubuntu's build pipeline, its cross-architecture ISA support strategy, and what RISC-V must satisfy to count as “enterprise ready”. The emphasis was on the RVA23 baseline and on consistency between firmware and the server platform specification.
Hot Chips 2026: progress on RISC-V standards and adoption
RISC-V International, SiFive and others updated on standards work and adoption at Hot Chips 2026, covering RVA23 deployment, progress on the server platform specification and core designs aimed at AI compute. It is the annual ecosystem progress round-up.
NVIDIA on RISC-V and GPU co-operation at Hot Chips 2026
In a Hot Chips 2026 tutorial session, NVIDIA described how CUDA applications combine CPU and GPU software modules, and the path to supporting its GPUs on RISC-V hosts. It connects to CUDA's official RISC-V support in 2025 and points to RISC-V servers becoming mainstream as GPU head nodes.
SiFive launches BigSky: the first enterprise-class 2U RISC-V server
SiFive announced the BigSky SF-2U870 data-center development platform, calling it the world's first enterprise-class, rack-mountable 2U RISC-V server; based on P870-D, it targets software porting and workload tuning for hyperscale customers. The Register notes that it is essentially a development and validation platform rather than a volume production machine.
Alibaba's C950 runs a 27-billion-parameter model on CPU alone
XuanTie C950 (64 cores, TSMC 5nm) ran Qwen3.8 27B with no GPU, no emulation layer and no translation overhead, reaching 30 tokens/s and 1.9 seconds to first token. For RISC-V servers this is a public validation of “a CPU carrying inference on its own”, and it reinforces confidence in the RISC-V AI-compute route in the Chinese market.
StarFive launches server-class RISC-V core Dubhe-100
StarFive announced Dubhe-100 (昉·天枢-100) for the server market: 15-stage pipeline, 6-issue, 256-entry reorder buffer, with RVA23 and vector extension support. The company calls it among China's first server-class RISC-V CPU IPs to reach a deliverable stage, and says customers are already using it to develop server chips.
Spain's Openchip launches BER10: Europe's first RISC-V chip for supercomputing
Openchip announced the 64-bit BER10, built on a sub-2nm GAA process and able to run full Linux, now open to companies and research institutions for validation in supercomputing and data-center projects. It is positioned as the base for European sovereign silicon and for follow-on AI accelerators.
Andes shuts down Condor Computing, ending its data-center-class RISC-V core plan
Jon Peddie Research reports that Andes has closed its subsidiary Condor Computing, with its RVA23 high-performance core IP returning to Andes. Condor's Cuzco used an unconventional temporally scheduled architecture and had been seen as an important attempt to push RISC-V into data centers; the shutdown is a setback for the ecosystem.
RISC-V's HPC roadmap comes into focus
Writing from an ISC 2026 panel discussion, HPCwire notes that more than 30 billion RISC-V cores have been deployed worldwide and that analysts expect the architecture to take a third of the market within five years, yet RISC-V has not delivered on expectations in HPC. The article expects that to change over the coming years as new chips ship and the ecosystem matures.
SUSE and Openchip partner to build an enterprise software stack for European RISC-V hardware
The two signed an MoU to adapt SUSE Linux Enterprise Server, RKE2, Rancher Prime and SUSE AI Factory to Openchip's RISC-V accelerators. The goal is a European sovereign technology stack running from chip architecture up to open-source software, which bears directly on RISC-V entering enterprise data centers.
StarFive and LECARC team up to develop RISC-V server CPUs
LECARC (Theo End Computing) will use StarFive's in-house Dubhe-100 CPU IP to develop next-generation server CPUs for the intelligent edge. Both sides cite a Bernstein report saying that agentic AI will raise the CPU share of inference workloads from about 14% in conventional large models to 50%.
Tenstorrent launches TT-Ascalon S and expands its Japan business
At TT-Deploy JP, Tenstorrent introduced the TT-Ascalon S RISC-V CPU IP for agentic AI, announced new performance records on language and video models, and joined Japanese ai&'s sovereign heterogeneous inference platform. Its Galaxy supercluster can be deployed standalone or alongside GPUs.
Report: Qualcomm said to be circling Tenstorrent in a $10 billion RISC-V power play
The Register reports that Qualcomm is in talks to acquire Tenstorrent at a valuation of about $10 billion. Tenstorrent owns the Ascalon RISC-V CPU IP and the Blackhole AI accelerator; if the deal goes through, Qualcomm would hold three RISC-V product lines at once — Ventana, Akeana and Tenstorrent.
SpacemiT K3 mini PC: a RVA23 desktop RISC-V that is “usable”
At the Ubuntu Summit, SpacemiT showed a mini PC built on the 16-core K3 SoC: RVA23 compliant and usable for everyday work, though not cheap. It shows that the RVA23 software baseline now has real hardware behind it, and it laid the groundwork for the server-class products that followed.
Firefly launches a 2880 TOPS RISC-V AI server
The Firefly CSC2-N48SPK3 packs 48 SpacemiT K3 nodes and 48 NVMe SSDs into a 4U chassis, with a nominal 2880 TOPS. This is the route of stacking RISC-V nodes into a “multi-node AI server” rather than relying on a single large chip.
Tenstorrent launches TT-QuietBox 2: a RISC-V AI workstation with a fully open stack
TT-QuietBox 2 (Blackhole) is a liquid-cooled desktop system that can run models of up to 120 billion parameters locally, with everything from compiler to kernel open source, starting at $9,999. The company calls it the first RISC-V-based desktop AI workstation to reach teraflop-class inference.
SiFive launches third-generation P570/P550 high-performance RISC-V IP
The new IP uses an out-of-order superscalar plus vector architecture aimed at area- and power-constrained consumer devices; SiFive calls P570 Gen3 the strongest and most efficient out-of-order core in its class. It is the latest generation of the P500 performance series and sits in a different product line from the data-center-oriented P870-D.
RISC-V Server Platform specification 1.0 formally ratified
The riscv-non-isa working group released RISC-V Server Platform v1.0, the specification's first formally ratified version, unifying minimum requirements for server systems in firmware, interrupt control, PCIe, RAS and related areas. For system vendors and cloud providers this is the precondition for RISC-V servers that can be installed and operated.
Tenstorrent Galaxy Blackhole server ships
Galaxy is a 6U chassis holding 32 Blackhole accelerators, interconnected by an Ethernet mesh with 100 Tbps of aggregate bandwidth, with 1TB of GDDR6 and 16TB of memory, at about $110,000 per system. The system is managed by RISC-V cores, making it a rare volume product at the AI-server system level for RISC-V.
SiFive closes a $400 million Series G at a $3.65 billion valuation
The round was led by Atreides Management with participation from NVIDIA, Apollo, Point72, T. Rowe Price and others, and the money will accelerate the data-center RISC-V roadmap. NVIDIA's investment was read as an endorsement of the RISC-V host CPU ecosystem.
Alibaba delivers a RISC-V server chip aimed at Chinese large models
DAMO Academy announced XuanTie C950, calling it the most powerful RISC-V processor yet: single-core SPECint2006 above 70 points, native support for hundred-billion-parameter models such as Qwen3 and DeepSeek V3, and RVA23.1 compliance. Outside assessments put its single-core performance near Apple's M1, while overall it still trails Western flagships, and the core count was not disclosed.
XuanTie C950 launches with native support for hundred-billion-parameter models
At the 2026 XuanTie RISC-V Ecosystem Conference in Shanghai, DAMO Academy announced the C950 (3.2GHz, 8-wide decode, 16-stage pipeline, an out-of-order window above 1000 entries) along with two RISC-V-native AI engines and native CoVE confidential computing support. The company cited SHD Group's forecast that RISC-V device shipments will reach 36 billion units in 2031.
openEuler 24.03 LTS SP3 RISC-V enters long-term maintenance
The release was led by the Institute of Software of the Chinese Academy of Sciences, working with ZTE, Alibaba DAMO Academy, SOPHGO, SpacemiT, UltraRISC and others; it is the first long-term-maintenance release with RVA23 support and preliminary support for the RISC-V Server Platform specification, while keeping both RVA20 and RVA23 baselines. For domestic RISC-V servers it is an operating system base that can be operated long term.
SpaceMiT K3: a 16-core RVA23 SoC, its specifications and early benchmarks
CNX Software rounded up the public K3 specifications — X100 cores, up to 2.5GHz, RVA23 compliant — and published early benchmark data. K3 later became the compute unit in several RISC-V servers and AI systems.
SiFive adopts NVIDIA NVLink Fusion
SiFive announced it is integrating NVLink Fusion into its high-performance data-center offerings, letting RISC-V host CPUs achieve coherent, high-bandwidth interconnect with NVIDIA GPUs and other accelerators. It is a key step for RISC-V to get into AI racks in the GPU head-node role.
2025
Qualcomm acquires Ventana Micro Systems
Qualcomm announced the acquisition of high-performance RISC-V CPU design company Ventana for an undisclosed sum, and will develop it alongside its own Arm Oryon cores. Ventana's Veyron V2 targets data centers and HPC, and the move is seen as Qualcomm's key fallback route outside Arm licensing.
Tenstorrent opens TT-Ascalon high-performance RISC-V CPU IP for licensing
Tenstorrent announced that TT-Ascalon is immediately available for customer licensing, pitched as a data-center-class RISC-V core customers can own and customize, with a complete delivery package. It pushes competition in RISC-V CPU IP from embedded up into the high-performance segment.
HPC is no longer an x86 monopoly as Arm and RISC-V move in
A The Register feature notes that Intel platforms have fallen from nearly 90% of the TOP500 a decade ago to 57%, with both Arm and RISC-V competing for HPC share. RISC-V's realistic opportunities lie mainly in accelerator control cores, sovereign supercomputing projects and specialized clusters.
Hands-on with the Tenstorrent QuietBox: solid compute, software stack holding it back
The roughly $12,000 RISC-V AI workstation scales up to a 32-chip server, but its software stack is immature and real-world tuning is hard. The review is an honest picture of RISC-V servers today: hardware first, software catching up.
Europe's first out-of-order RISC-V processor taped out successfully
The eProcessor project announced the development and deployment of Europe's first out-of-order RISC-V processor, built on a 22nm process. It is part of the European Processor Initiative (EPI) and builds design and validation capability for later HPC chips.
Meta acquires Rivos to accelerate its in-house compute engine
Meta acquired RISC-V server chip startup Rivos, folding its team and IP into Meta's Compute Engine organization. The Next Platform reads it as confirmation of the hyperscaler route of building custom CPUs on RISC-V, and as evidence that Rivos' server-class design had real engineering value.
Condor's Cuzco: pushing RISC-V into the data center
The Next Platform analysed Condor Computing's Cuzco core — a temporally scheduled, high-performance RVA23 design aimed at competing head-on with Arm Neoverse in the data center. The article also notes that software and ecosystem maturity remain the biggest variables.
Hot Chips 2025: Condor's Cuzco high-performance RISC-V design
ServeTheHome reported the microarchitectural details of Cuzco on site, calling it a rare high-performance RISC-V core at Hot Chips — wide issue, deeply out-of-order, aimed at server-class workloads. The core was later discontinued when Condor was shut down.
NVIDIA brings CUDA to RISC-V
NVIDIA officially extended CUDA software stack support to RISC-V CPUs, with the first beneficiaries being China's new generation of RISC-V server chips. For RISC-V servers this fills in the most critical missing piece of the AI ecosystem and makes RISC-V better suited to being a GPU head node.
GlobalFoundries acquires MIPS
GlobalFoundries acquired chip design company MIPS, creating an entity with both design and manufacturing capability and explicitly betting on RISC-V's opportunity in the AI market. MIPS had shifted its product line to RISC-V in recent years, and the deal strengthens its presence in the licensed-core market.
openEuler Developer Day 2025: what the RISC-V SIG is working on
The RISC-V track was hosted by the openEuler RISC-V SIG with participation from the Institute of Software of the Chinese Academy of Sciences, the Beijing Institute of Open Source Chip and Alibaba, discussing server software stacks, distribution maintenance and hardware enablement. It is a record of progress in the domestic RISC-V server operating system ecosystem.
Europe's DARE project launches: €240 million for RISC-V supercomputing chips
38 organisations jointly formed DARE (Digital Autonomy with RISC-V in Europe), planning to develop three HPC- and AI-oriented chiplets over three years on a budget of about €240 million. The goal is to give European supercomputing a non-US processor option, and it is Europe's largest single investment in sovereign RISC-V compute.
Alibaba launches server-class RISC-V core C930
XuanTie C930 targets servers, PCs and autonomous driving with a 6-wide decode, 16-stage out-of-order microarchitecture, RVA23 compliance and support for Vector, CoVE, RAS, AIA and other extensions. Reports at the same time said China would issue a policy document promoting nationwide RISC-V use, putting policy and product behind the same push.
SOPHGO launches the world's first RISC-V many-core server with DeepSeek support
At the 2025 China RISC-V Ecosystem Conference, SOPHGO announced the SRA3-40 compute server based on the 64-core SG2044, alongside the SRB3-40 storage server and SRM3-40 converged server. Firefly launched server products based on the previous-generation SG2042 at the same time, marking the point where RISC-V many-core systems began to form a coherent lineup.
SOPHGO launches heterogeneous converged products, advancing RISC-V server systems
At the 2025 China RISC-V Ecosystem Conference, SOPHGO announced SG2044 with companion servers and AI compute products, emphasizing heterogeneous convergence of CPU and in-house TPU for AI computing centers, general-purpose compute and edge scenarios. It is a system-level upgrade of the domestic RISC-V server platform after SG2042.
US adds SOPHGO to the Entity List
The US Commerce Department added Chinese RISC-V chip design company SOPHGO (Sophgo) to the Entity List on suspicion of supplying AI chips to Huawei. For the RISC-V server supply chain this is the most direct case of geopolitical risk, and it affects the company's overseas foundry access and customer expansion.
Third-generation XiangShan processor to debut in 2025
Bao Yungang of the Institute of Computing Technology, Chinese Academy of Sciences, previewed on Weibo that the third-generation XiangShan design would be delivered in 2025, with performance possibly approaching Arm's Neoverse N2 for HPC and data-center potential. XiangShan is the flagship open-source high-performance RISC-V core project and the technical origin of commercial chips such as SpacemiT's V100.
Newest first. Items published on the same day are not ranked against each other; anything with a real effect on server-class RISC-V is marked as key. No second-hand interpretation — reader decides.