http://riscvservers.org/en/news/Each item carries a summary and a link to the original, all checked to openenSun, 01 Nov 2026 09:39:37 +0000Hugohttps://www.design-reuse.com/news/202531315-qualcomm-buys-risc-v-startup-akeana-to-push-into-ai-and-data-center-chipsnews:https://www.design-reuse.com/news/202531315-qualcomm-buys-risc-v-startup-akeana-to-push-into-ai-and-data-center-chipsThu, 22 Oct 2026 00:00:00 +0800Qualcomm has completed its acquisition of RISC-V processor design company Akeana; the deal value was not disclosed, and Akeana's IP and engineering team moved into Qualcomm wholesale to strengthen its AI and data-center position. Akeana was founded in 2021 by a team that had worked on server chips at Marvell, raised more than $100 million in August 2024, and focuses on customer-customizable RISC-V cores. It is the second time Qualcomm has taken a data-center-class RISC-V asset in-house, after Ventana.（Design & Reuse / Dealroom）M&A and investmentChip launchhttps://wap.eastmoney.com/a/202610213903006416.htmlnews:https://wap.eastmoney.com/a/202610213903006416.htmlWed, 21 Oct 2026 00:00:00 +0800At the 2026 RISC-V China Summit, Lanxin Computing launched a Zhitong fusion supernode, extending its LX500-based RISC-V AI compute from a single chip and server to cluster-level infrastructure. LX500 integrates 48 RISC-V cores (32 performance, 16 efficiency) with AI vector and matrix engines for 75 TOPS INT8, shares DDR5 through a unified memory architecture and supports CXL, tuned for time-to-first-token, prefill and long-context inference. The lineup now spans the LX500 chip, the Lenovo Wentian WR5219 G5 server, the LX5000 all-in-one and the supernode, and the company says Qwen, DeepSeek and Kimi models are already adapted — RISC-V servers are starting to ship as a full chip-system-cluster stack.（Shanghai Observer / Eastmoney）Systems & boardsHPChttps://tech.ifeng.com/c/8xNZKmD2pZDnews:https://tech.ifeng.com/c/8xNZKmD2pZDTue, 20 Oct 2026 00:00:00 +0800At the 2026 RISC-V China Summit, UltraRISC disclosed UR-CP400, a high-performance RISC-V core IP compliant with RVA23 and RVV 1.0, using an 8-wide out-of-order, 14-stage pipeline and exceeding 22 SPECint_base2006 points/GHz in FPGA configuration, with enhancements for multi-tenant cloud virtualization and agentic workloads; delivery is planned for Q1 2027. UltraRISC offers both core IP and multi-core CPUs, and UR-CP400's figures approach first-tier server cores, but commercial silicon is still a year out.（ITHome / Phoenix Tech）Chip launchhttps://news.qq.com/rain/a/20261020A05R3V00news:https://news.qq.com/rain/a/20261020A05R3V00Tue, 20 Oct 2026 00:00:00 +0800At the 2026 RISC-V China Summit, DAMO Academy chief scientist Meng Jianyi reported that cumulative XuanTie RISC-V shipments have passed 6 billion units, that the server-class C950 core is based on RVA23 and exceeds 70 SPECint2006 points per core, and outlined a processor roadmap aimed at autonomous driving and embodied AI. DAMO stressed hardware-software co-design to move products from usable to mass-producible. For the server market, C950 is one of the few Chinese RISC-V core IPs explicitly aimed at general-purpose data-center compute, and the shipment scale shows the XuanTie ecosystem can support high-end products.（ICSmart / Tencent News）Ecosystem partnershipsHPChttps://view.inews.qq.com/a/20261020A0BL9500news:https://view.inews.qq.com/a/20261020A0BL9500Tue, 20 Oct 2026 00:00:00 +0800At the 2026 RISC-V China Summit in Shenzhen, SpacemiT launched its first server-class chip, the V100: 6 XiangShan “Kunminghu” V2R2 high-performance cores plus 40 in-house X100 efficiency cores, 46 cores in total, scalable to 92 cores across two sockets, with 8-channel DDR5 and 52 PCIe 5.0 lanes. The company calls it the industry's first compute chip fully compliant with the RISC-V server specification, with all BRS tests passed and distributions such as openEuler, openKylin, Ubuntu, Debian and Fedora installing and booting directly. It is the first time a XiangShan core has gone into a commercial server chip, and it means RISC-V servers are starting to offer general-purpose distribution delivery.（Tencent News / 芯智讯 (ICSmart)）Chip launchServer shipmentsStandards & specshttps://news.qq.com/rain/a/20261019A09YLY00news:https://news.qq.com/rain/a/20261019A09YLY00Mon, 19 Oct 2026 00:00:00 +0800At the 2026 RISC-V China Summit, Lirui Micro, a subsidiary of ZTE Microelectronics, showed Zhufeng 200, a high-performance RISC-V CPU for AI data centers. The chip is based on RVA23 with Hypervisor, AIA, CoVE and RVV 1.0 support, uses a 64-bit superscalar out-of-order architecture, integrates vector/matrix plus compression and crypto engines, and supports DDR5 (including MRDIMM), PCIe 6.0 and CXL 3. It targets agent clusters, inference supernode host CPUs and enterprise hybrid inference; the company says it can run 100-billion-parameter MoE models, with detailed specifications due by the end of 2026. It is the first time a carrier-affiliated Chinese chip company has positioned RISC-V explicitly as a data-center host CPU.（ICSmart / Tencent News）Chip launchhttps://tenstorrent.com/en/newsroom/tenstorrent-announces-series-enews:https://tenstorrent.com/en/newsroom/tenstorrent-announces-series-eMon, 19 Oct 2026 00:00:00 +0800Tenstorrent closed a $1.5 billion Series E at a $6.2 billion post-money valuation, led by Trace Capital and Innovation X with participation from ARK Invest, Fidelity, Morgan Stanley, Sandisk and Tether Investments, among others. The company says the capital will fund volume deployment of Galaxy servers, expand inference services for open-weight models, and advance the AI and CPU IP it licenses. Tenstorrent pairs RISC-V CPUs (TT-Ascalon) with in-house Tensix AI cores across a stack that runs from a single card to superclusters, and the round adds manufacturing and delivery capacity to its data-center competition with NVIDIA.（Tenstorrent）M&A and investmenthttps://www.nextplatform.com/compute/2026/10/15/a-decade-in-zerorisc-sees-a-bright-future-for-open-silicon/5303297news:https://www.nextplatform.com/compute/2026/10/15/a-decade-in-zerorisc-sees-a-bright-future-for-open-silicon/5303297Thu, 15 Oct 2026 00:00:00 +0800The Next Platform interviewed zeroRISC founder Dominic Rizzo about the decade in which he went from Google's OpenTitan project to commercializing open-source silicon. The company enters server security through an open-source Root of Trust and argues that open silicon has distinct value for confidential computing and supply-chain trust. The piece is ecosystem observation, not a product announcement.（The Next Platform）Ecosystem partnershipsSoftware stackhttps://www.sifive.com/press/sifive-amd-rocm-riscv-datacenter-serversnews:https://www.sifive.com/press/sifive-amd-rocm-riscv-datacenter-serversTue, 15 Sep 2026 00:00:00 +0800At the AI Infra Summit, SiFive and AMD demonstrated ROCm 10.0 running on the SiFive BigSky platform: a P870-D as head node with a Radeon AI PRO R9700 handling inference offload, running the Gemma4-E2B model. Both companies said they will keep optimizing ROCm performance on RISC-V servers. It is the first time RISC-V servers have appeared in the official partnership view of a mainstream GPU software stack.（SiFive）Software stackEcosystem partnershipsHPChttps://www.servethehome.com/canonical-evolution-of-enterprise-open-source-risc-v-at-hot-chips-2026/news:https://www.servethehome.com/canonical-evolution-of-enterprise-open-source-risc-v-at-hot-chips-2026/Mon, 07 Sep 2026 00:00:00 +0800At Hot Chips 2026, Canonical silicon alliances director Gordan Markuš walked through Ubuntu's build pipeline, its cross-architecture ISA support strategy, and what RISC-V must satisfy to count as “enterprise ready”. The emphasis was on the RVA23 baseline and on consistency between firmware and the server platform specification.（ServeTheHome）Operating systemsSoftware stackhttps://www.servethehome.com/update-on-risc-v-standards-and-adoption-at-hot-chips-2026/news:https://www.servethehome.com/update-on-risc-v-standards-and-adoption-at-hot-chips-2026/Wed, 02 Sep 2026 00:00:00 +0800RISC-V International, SiFive and others updated on standards work and adoption at Hot Chips 2026, covering RVA23 deployment, progress on the server platform specification and core designs aimed at AI compute. It is the annual ecosystem progress round-up.（ServeTheHome）Standards & specsEcosystem partnershipshttps://www.servethehome.com/nvidia-risc-v-for-nvidia-gpus-at-hot-chips-2026/news:https://www.servethehome.com/nvidia-risc-v-for-nvidia-gpus-at-hot-chips-2026/Tue, 01 Sep 2026 00:00:00 +0800In a Hot Chips 2026 tutorial session, NVIDIA described how CUDA applications combine CPU and GPU software modules, and the path to supporting its GPUs on RISC-V hosts. It connects to CUDA's official RISC-V support in 2025 and points to RISC-V servers becoming mainstream as GPU head nodes.（ServeTheHome）Software stackEcosystem partnershipshttps://www.theregister.com/systems/2026/08/25/sifive-pushes-development-server-to-take-risc-v-into-the-datacenter/5292136news:https://www.theregister.com/systems/2026/08/25/sifive-pushes-development-server-to-take-risc-v-into-the-datacenter/5292136Tue, 25 Aug 2026 00:00:00 +0800SiFive announced the BigSky SF-2U870 data-center development platform, calling it the world's first enterprise-class, rack-mountable 2U RISC-V server; based on P870-D, it targets software porting and workload tuning for hyperscale customers. The Register notes that it is essentially a development and validation platform rather than a volume production machine.（The Register）Server shipmentsSystems & boardsSoftware stackhttps://www.design-reuse.com/news/202531019-alibaba-s-risc-v-chip-runs-27b-ai-model-without-a-gpu/news:https://www.design-reuse.com/news/202531019-alibaba-s-risc-v-chip-runs-27b-ai-model-without-a-gpu/Mon, 24 Aug 2026 00:00:00 +0800XuanTie C950 (64 cores, TSMC 5nm) ran Qwen3.8 27B with no GPU, no emulation layer and no translation overhead, reaching 30 tokens/s and 1.9 seconds to first token. For RISC-V servers this is a public validation of “a CPU carrying inference on its own”, and it reinforces confidence in the RISC-V AI-compute route in the Chinese market.（Design & Reuse / Intelligent Living）Chip launchSoftware stackhttps://www.design-reuse.com/news/202531000-starfive-launches-server-class-risc-v-ip-to-accelerate-its-strategic-expansion-into-ai-computing-infrastructure/news:https://www.design-reuse.com/news/202531000-starfive-launches-server-class-risc-v-ip-to-accelerate-its-strategic-expansion-into-ai-computing-infrastructure/Thu, 20 Aug 2026 00:00:00 +0800StarFive announced Dubhe-100 (昉·天枢-100) for the server market: 15-stage pipeline, 6-issue, 256-entry reorder buffer, with RVA23 and vector extension support. The company calls it among China's first server-class RISC-V CPU IPs to reach a deliverable stage, and says customers are already using it to develop server chips.（Design & Reuse）Chip launchServer shipmentshttps://www.design-reuse.com/news/202530985-spain-unveils-ber10-europe-s-first-risc-v-chip-for-supercomputing/news:https://www.design-reuse.com/news/202530985-spain-unveils-ber10-europe-s-first-risc-v-chip-for-supercomputing/Mon, 17 Aug 2026 00:00:00 +0800Openchip announced the 64-bit BER10, built on a sub-2nm GAA process and able to run full Linux, now open to companies and research institutions for validation in supercomputing and data-center projects. It is positioned as the base for European sovereign silicon and for follow-on AI accelerators.（Design & Reuse / russpain）Chip launchHPChttps://www.jonpeddie.com/news/condor-flies-no-morenews:https://www.jonpeddie.com/news/condor-flies-no-moreThu, 13 Aug 2026 00:00:00 +0800Jon Peddie Research reports that Andes has closed its subsidiary Condor Computing, with its RVA23 high-performance core IP returning to Andes. Condor's Cuzco used an unconventional temporally scheduled architecture and had been seen as an important attempt to push RISC-V into data centers; the shutdown is a setback for the ecosystem.（Jon Peddie Research）M&A and investmentChip launchhttps://www.design-reuse.com/news/202530880-charting-risc-v-s-future-in-hpc/news:https://www.design-reuse.com/news/202530880-charting-risc-v-s-future-in-hpc/Mon, 27 Jul 2026 00:00:00 +0800Writing from an ISC 2026 panel discussion, HPCwire notes that more than 30 billion RISC-V cores have been deployed worldwide and that analysts expect the architecture to take a third of the market within five years, yet RISC-V has not delivered on expectations in HPC. The article expects that to change over the coming years as new chips ship and the ecosystem matures.（Design & Reuse / HPCwire）HPCEcosystem partnershipshttps://www.design-reuse.com/news/202530790-suse-openchip-partner-to-develop-european-risc-v-hardware/news:https://www.design-reuse.com/news/202530790-suse-openchip-partner-to-develop-european-risc-v-hardware/Thu, 09 Jul 2026 00:00:00 +0800The two signed an MoU to adapt SUSE Linux Enterprise Server, RKE2, Rancher Prime and SUSE AI Factory to Openchip's RISC-V accelerators. The goal is a European sovereign technology stack running from chip architecture up to open-source software, which bears directly on RISC-V entering enterprise data centers.（Design & Reuse / Evertiq）Software stackEcosystem partnershipsOperating systemshttps://www.design-reuse.com/news/202530748-starfive-and-lecarc-forge-partnership-to-co-develop-risc-v-server-cpus-and-seize-new-opportunities-in-the-agentic-ai-era/news:https://www.design-reuse.com/news/202530748-starfive-and-lecarc-forge-partnership-to-co-develop-risc-v-server-cpus-and-seize-new-opportunities-in-the-agentic-ai-era/Thu, 02 Jul 2026 00:00:00 +0800LECARC (Theo End Computing) will use StarFive's in-house Dubhe-100 CPU IP to develop next-generation server CPUs for the intelligent edge. Both sides cite a Bernstein report saying that agentic AI will raise the CPU share of inference workloads from about 14% in conventional large models to 50%.（Design & Reuse）Ecosystem partnershipsChip launchhttps://tenstorrent.com/en/newsroom/tenstorrent-sets-new-performance-records-launches-tt--ascalon-snews:https://tenstorrent.com/en/newsroom/tenstorrent-sets-new-performance-records-launches-tt--ascalon-sTue, 30 Jun 2026 00:00:00 +0800At TT-Deploy JP, Tenstorrent introduced the TT-Ascalon S RISC-V CPU IP for agentic AI, announced new performance records on language and video models, and joined Japanese ai&'s sovereign heterogeneous inference platform. Its Galaxy supercluster can be deployed standalone or alongside GPUs.（Tenstorrent）Chip launchEcosystem partnershipshttps://www.theregister.com/systems/2026/06/16/qualcomm-said-to-be-circling-ai-chip-biz-tenstorrent-in-10b-risc-v-power-play/5256084news:https://www.theregister.com/systems/2026/06/16/qualcomm-said-to-be-circling-ai-chip-biz-tenstorrent-in-10b-risc-v-power-play/5256084Tue, 16 Jun 2026 00:00:00 +0800The Register reports that Qualcomm is in talks to acquire Tenstorrent at a valuation of about $10 billion. Tenstorrent owns the Ascalon RISC-V CPU IP and the Blackhole AI accelerator; if the deal goes through, Qualcomm would hold three RISC-V product lines at once — Ventana, Akeana and Tenstorrent.（The Register）M&A and investmenthttps://www.theregister.com/systems/2026/06/10/spacemit-shows-off-usably-quick-risc-v-mini-desktop/5252935news:https://www.theregister.com/systems/2026/06/10/spacemit-shows-off-usably-quick-risc-v-mini-desktop/5252935Wed, 10 Jun 2026 00:00:00 +0800At the Ubuntu Summit, SpacemiT showed a mini PC built on the 16-core K3 SoC: RVA23 compliant and usable for everyday work, though not cheap. It shows that the RVA23 software baseline now has real hardware behind it, and it laid the groundwork for the server-class products that followed.（The Register）Chip launchSystems & boardshttps://www.cnx-software.com/2026/05/20/firefly-csc2-n48spk3-a-2880-tops-risc-v-ai-server-with-48-spacemit-k3-nodes-48-nvme-ssds/news:https://www.cnx-software.com/2026/05/20/firefly-csc2-n48spk3-a-2880-tops-risc-v-ai-server-with-48-spacemit-k3-nodes-48-nvme-ssds/Wed, 20 May 2026 00:00:00 +0800The Firefly CSC2-N48SPK3 packs 48 SpacemiT K3 nodes and 48 NVMe SSDs into a 4U chassis, with a nominal 2880 TOPS. This is the route of stacking RISC-V nodes into a “multi-node AI server” rather than relying on a single large chip.（CNX Software）Server shipmentsSystems & boardshttps://www.design-reuse.com/news/202530525-tenstorrent-unveils-tt-quietbox-2-the-first-risc-v-ai-workstation-with-a-fully-open-source-stack-to-deliver-teraflop-class-inference/news:https://www.design-reuse.com/news/202530525-tenstorrent-unveils-tt-quietbox-2-the-first-risc-v-ai-workstation-with-a-fully-open-source-stack-to-deliver-teraflop-class-inference/Mon, 18 May 2026 00:00:00 +0800TT-QuietBox 2 (Blackhole) is a liquid-cooled desktop system that can run models of up to 120 billion parameters locally, with everything from compiler to kernel open source, starting at $9,999. The company calls it the first RISC-V-based desktop AI workstation to reach teraflop-class inference.（Design & Reuse / Tenstorrent）Systems & boardsSoftware stackhttps://www.sifive.com/press/sifive-sets-new-bar-for-high-performance-risc-v-with-third-generation-performance-p550-and-p570-ipnews:https://www.sifive.com/press/sifive-sets-new-bar-for-high-performance-risc-v-with-third-generation-performance-p550-and-p570-ipTue, 12 May 2026 00:00:00 +0800The new IP uses an out-of-order superscalar plus vector architecture aimed at area- and power-constrained consumer devices; SiFive calls P570 Gen3 the strongest and most efficient out-of-order core in its class. It is the latest generation of the P500 performance series and sits in a different product line from the data-center-oriented P870-D.（SiFive）Chip launchhttps://github.com/riscv-non-isa/riscv-server-platform/releases/tag/v1.0news:https://github.com/riscv-non-isa/riscv-server-platform/releases/tag/v1.0Wed, 06 May 2026 00:00:00 +0800The riscv-non-isa working group released RISC-V Server Platform v1.0, the specification's first formally ratified version, unifying minimum requirements for server systems in firmware, interrupt control, PCIe, RAS and related areas. For system vendors and cloud providers this is the precondition for RISC-V servers that can be installed and operated.（RISC-V International (GitHub)）Standards & specshttps://tenstorrent.com/en/newsroom/tenstorrent-enables-ai-at-scale-with-industry-leading-performancenews:https://tenstorrent.com/en/newsroom/tenstorrent-enables-ai-at-scale-with-industry-leading-performanceWed, 29 Apr 2026 00:00:00 +0800Galaxy is a 6U chassis holding 32 Blackhole accelerators, interconnected by an Ethernet mesh with 100 Tbps of aggregate bandwidth, with 1TB of GDDR6 and 16TB of memory, at about $110,000 per system. The system is managed by RISC-V cores, making it a rare volume product at the AI-server system level for RISC-V.（Tenstorrent）Server shipmentsSystems & boardshttps://www.sifive.com/press/sifive-raises-400-million-to-accelerate-high-performance-risc-v-data-center-solutionsnews:https://www.sifive.com/press/sifive-raises-400-million-to-accelerate-high-performance-risc-v-data-center-solutionsThu, 09 Apr 2026 00:00:00 +0800The round was led by Atreides Management with participation from NVIDIA, Apollo, Point72, T. Rowe Price and others, and the money will accelerate the data-center RISC-V roadmap. NVIDIA's investment was read as an endorsement of the RISC-V host CPU ecosystem.（SiFive）M&A and investmenthttps://www.theregister.com/on-prem/2026/03/25/alibaba-delivers-risc-v-server-chip-optimized-for-chinese-ai/5229685news:https://www.theregister.com/on-prem/2026/03/25/alibaba-delivers-risc-v-server-chip-optimized-for-chinese-ai/5229685Wed, 25 Mar 2026 00:00:00 +0800DAMO Academy announced XuanTie C950, calling it the most powerful RISC-V processor yet: single-core SPECint2006 above 70 points, native support for hundred-billion-parameter models such as Qwen3 and DeepSeek V3, and RVA23.1 compliance. Outside assessments put its single-core performance near Apple's M1, while overall it still trails Western flagships, and the core count was not disclosed.（The Register）Chip launchServer shipmentshttps://www3.xinhuanet.com/tech/20260324/fdc7c3b201074147a46b5ce6ad51045f/c.htmlnews:https://www3.xinhuanet.com/tech/20260324/fdc7c3b201074147a46b5ce6ad51045f/c.htmlTue, 24 Mar 2026 00:00:00 +0800At the 2026 XuanTie RISC-V Ecosystem Conference in Shanghai, DAMO Academy announced the C950 (3.2GHz, 8-wide decode, 16-stage pipeline, an out-of-order window above 1000 entries) along with two RISC-V-native AI engines and native CoVE confidential computing support. The company cited SHD Group's forecast that RISC-V device shipments will reach 36 billion units in 2031.（Xinhua News (新华网)）Chip launchEcosystem partnershipshttps://www.openeuler.org/zh/blog/20260317-RISC-V/20260317-RISC-V.htmlnews:https://www.openeuler.org/zh/blog/20260317-RISC-V/20260317-RISC-V.htmlMon, 09 Mar 2026 00:00:00 +0800The release was led by the Institute of Software of the Chinese Academy of Sciences, working with ZTE, Alibaba DAMO Academy, SOPHGO, SpacemiT, UltraRISC and others; it is the first long-term-maintenance release with RVA23 support and preliminary support for the RISC-V Server Platform specification, while keeping both RVA20 and RVA23 baselines. For domestic RISC-V servers it is an operating system base that can be operated long term.（openEuler community (openEuler 社区)）Operating systemsSoftware stackStandards & specshttps://www.cnx-software.com/2026/01/23/spacemit-k3-16-core-risc-v-soc-system-information-and-early-benchmarks/news:https://www.cnx-software.com/2026/01/23/spacemit-k3-16-core-risc-v-soc-system-information-and-early-benchmarks/Fri, 23 Jan 2026 00:00:00 +0800CNX Software rounded up the public K3 specifications — X100 cores, up to 2.5GHz, RVA23 compliant — and published early benchmark data. K3 later became the compute unit in several RISC-V servers and AI systems.（CNX Software）Chip launchhttps://www.theregister.com/on-prem/2026/01/15/sifive-to-fuse-risc-v-with-nvidias-nvlink/5115896news:https://www.theregister.com/on-prem/2026/01/15/sifive-to-fuse-risc-v-with-nvidias-nvlink/5115896Thu, 15 Jan 2026 00:00:00 +0800SiFive announced it is integrating NVLink Fusion into its high-performance data-center offerings, letting RISC-V host CPUs achieve coherent, high-bandwidth interconnect with NVIDIA GPUs and other accelerators. It is a key step for RISC-V to get into AI racks in the GPU head-node role.（The Register）Ecosystem partnershipsHPChttps://www.theregister.com/special-features/2025/12/10/qualcomm-takes-risc-on-arm-alternative-with-ventana-buy/2292187news:https://www.theregister.com/special-features/2025/12/10/qualcomm-takes-risc-on-arm-alternative-with-ventana-buy/2292187Wed, 10 Dec 2025 00:00:00 +0800Qualcomm announced the acquisition of high-performance RISC-V CPU design company Ventana for an undisclosed sum, and will develop it alongside its own Arm Oryon cores. Ventana's Veyron V2 targets data centers and HPC, and the move is seen as Qualcomm's key fallback route outside Arm licensing.（The Register）M&A and investmenthttps://tenstorrent.com/en/newsroom/tenstorrent-announces-availability-of-tt-ascalonnews:https://tenstorrent.com/en/newsroom/tenstorrent-announces-availability-of-tt-ascalonThu, 04 Dec 2025 00:00:00 +0800Tenstorrent announced that TT-Ascalon is immediately available for customer licensing, pitched as a data-center-class RISC-V core customers can own and customize, with a complete delivery package. It pushes competition in RISC-V CPU IP from embedded up into the high-performance segment.（Tenstorrent）Chip launchhttps://www.theregister.com/special-features/2025/11/27/hpc-wont-be-x86-forever-and-its-starting-to-show/2154107news:https://www.theregister.com/special-features/2025/11/27/hpc-wont-be-x86-forever-and-its-starting-to-show/2154107Thu, 27 Nov 2025 00:00:00 +0800A The Register feature notes that Intel platforms have fallen from nearly 90% of the TOP500 a decade ago to 57%, with both Arm and RISC-V competing for HPC share. RISC-V's realistic opportunities lie mainly in accelerator control cores, sovereign supercomputing projects and specialized clusters.（The Register）HPChttps://www.theregister.com/on-prem/2025/11/27/blackhole-quietbox-tenstorrents-ai-workstation-reviewed/2113269news:https://www.theregister.com/on-prem/2025/11/27/blackhole-quietbox-tenstorrents-ai-workstation-reviewed/2113269Thu, 27 Nov 2025 00:00:00 +0800The roughly $12,000 RISC-V AI workstation scales up to a 32-chip server, but its software stack is immature and real-world tuning is hard. The review is an honest picture of RISC-V servers today: hardware first, software catching up.（The Register）Systems & boardsSoftware stackhttps://riscv.org/blog/europe-achieves-a-key-milestone-with-the-europes-first-out-of-order-risc-v-processor-chip-with-the-eprocessnews:https://riscv.org/blog/europe-achieves-a-key-milestone-with-the-europes-first-out-of-order-risc-v-processor-chip-with-the-eprocessThu, 09 Oct 2025 00:00:00 +0800The eProcessor project announced the development and deployment of Europe's first out-of-order RISC-V processor, built on a 22nm process. It is part of the European Processor Initiative (EPI) and builds design and validation capability for later HPC chips.（RISC-V International）HPCChip launchhttps://www.nextplatform.com/compute/2025/10/02/meta-buys-rivos-to-accelerate-compute-engine-engineering/1642477news:https://www.nextplatform.com/compute/2025/10/02/meta-buys-rivos-to-accelerate-compute-engine-engineering/1642477Thu, 02 Oct 2025 00:00:00 +0800Meta acquired RISC-V server chip startup Rivos, folding its team and IP into Meta's Compute Engine organization. The Next Platform reads it as confirmation of the hyperscaler route of building custom CPUs on RISC-V, and as evidence that Rivos' server-class design had real engineering value.（The Next Platform）M&A and investmentChip launch