Servers

蓝芯算力（深圳）科技有限公司 · Lanxin Computing (Shenzhen) Technology Co., Ltd.

SoC / processor

LX500 single die: 48 heterogeneous cores = 32 performance cores + 16 efficiency cores (sharing the on-die memory space); an AI matrix engine integrated on-die, peak 75 TOPS INT8, supporting INT4/INT8/FP16/FP32; RVV 1.0 and RVA23 support; matrix-multiply extension instructions plus dedicated matrix-arithmetic hardware units.

Form factor

The chip is a single-die package (package type and dimensions not disclosed); the complete system is a 2U rack server (Lenovo WenTian WR5219 G5).

Memory

4-channel DDR5, up to 6400 MT/s; unified memory between the CPU and the on-die AI engine (one shared memory space, zero data movement); CXL 2.0 memory expansion supported.

Storage and I/O

64 PCIe Gen5 lanes (with bifurcation support) + 4 PCIe Gen3 lanes; CXL 2.0; the complete system (WR5219 G5) offers multiple storage/IO/memory options and supports hot-swap drives.

Official OS

Ubuntu, openEuler (the official bring-up demo booted on real hardware under both); China Mobile's BC-Linux has completed in-depth adaptation.

Where to get it

No pricing announced for either the chip or the system; the system ships through Lenovo's WenTian product line

First shown

2026-02

Official positioning: the world's first server-oriented RISC-V + AI “convergence” CPU (flagship product), putting general-purpose compute and on-die AI inference on the same chip in place of a “CPU + discrete accelerator card” pairing; the host system is the 2U rack server Lenovo WenTian WR5219 G5, with all-in-one and converged super-node form factors also offered.

进迭时空（北京）智能科技有限公司 · SpacemiT

SoC / processor

V100 single die: 46 heterogeneous cores = 6× XiangShan Kunminghu V2R2 (up to 2.1 GHz, single-core SPECint2006 ≥15.0/GHz) + 40× in-house SpacemiT X100 (up to 2.4 GHz, ≥9.0/GHz); RVA23; 64 MB SLC; dual-socket coherent interconnect scaling to 92 cores.

Form factor

FCBGA package, 58.5 × 75.4 mm, 0.94 mm pitch; the C2201 system is a 2U rack unit, 820×447.4×87.8 mm, ≤35 kg (G5201 4U 895×447.4×176.8 mm; S5236 4U).

Memory

8-channel DDR5, 1DPC, DDR5 RDIMM, 4800 MT/s, 307 GB/s peak bandwidth per chip; up to 256 GB per DIMM, up to 2 TB per chip; the C2201 system has 16 DIMM slots and supports up to 2 TB.

Storage and I/O

52 PCIe 5.0 lanes in total (flexible x16–x1 configuration, expandable with AI cards and SAS/SATA/NVMe); 1×GMAC (IEEE 1588); peripherals 1×QSPI, 1×LPC, 1×eSPI, 3×SPI master, 4×I3C, 12×I2C, 12×SMBUS, 5×UART. C2201 system: 88 PCIe 5.0 lanes across two sockets, 8×3.5" U.2 NVMe front-accessible, 1×M.2 internal, 2×2.5" SATA rear.

Power

Chip TDP 120W (official datasheet); the C2201 system ships with 1600W CRPS Platinum power supplies in 1+1 redundancy.

Official OS

openEuler, openRuyi, openKylin, Debian, Ubuntu (26.10), Red Hat Enterprise Linux 10.2 (developer preview), Fedora, Rocky Linux — all directly installable and bootable; firmware UEFI 2.1.1 + ACPI 6.6, EDK2, openBMC; virtualization KVM/QEMU, Docker.

Where to get it

No pricing or volume-production date announced; companion systems C2201 / G5201 / S5236

First shown

2026-10

Official positioning: the first compute chip / server-class CPU fully compliant with the RISC-V server specification, aimed at general-purpose data-center compute, agent infrastructure and domestically developed AI computing platforms; launched alongside the C2201 compute server (2U, dual-socket), G5201 AI server (4U, 8 cards) and S5236 storage server (4U, 36 bays).